With the scaling down of integrated circuits, metal-oxide-semiconductor (MOS) devices are becoming increasingly smaller. The junction depths of the MOS devices are also reduced accordingly, which causes technical difficulties for the formation processes. For example, small MOS devices demand high impurity concentrations in source/drain regions and lightly doped source and drain (LDD) regions in order to reduce sheet resistances. However, it is difficult to increase implantation dosages without causing the adverse increase in junction depth.
Conventionally, arsenic is implanted in the formation of LDD regions. Arsenic has a relatively low diffusion length, and thus can be implanted to a high concentration without significantly affecting short channel characteristics and junction abruptness. However, arsenic has a low activation rate. Accordingly, the sheet resistances of arsenic-doped LDD regions are high. On the other hand, phosphorus has a high activation rate. However, the corresponding junction depths of phosphorus-doped LDD regions are greater than that of arsenic-doped LDD regions. Therefore, designers have to compromise between high activation rate and shallow junction depths.
For MOS devices, their threshold voltages Vt and drain-induced barrier lowering (DIBL) are sensitive to the junction depths. Deep LDD junctions may cause the degradation in device performance, and even device failure. For example, the linear threshold voltages Vt of the MOS devices having deep LDD junctions may be too low, and thus the MOS devices may be turned on with little, or even no gate voltages applied. Also, the DIBL of the MOS devices may be lowered to practically 0 mV/V, indicating the occurrence of device punch through. Accordingly, a new method for reducing the junction depths of MOS devices is needed.